Which signal of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP should be used to determine when it's safe to start interacting with the AXI bus interface?

Description

When using the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP, you may see the AXI wready signal getting asserted during calibration but it is not safe to interact yet. You should wait until the local_cal_success signal gets asserted before you start interacting with the AXI bus interface.

Resolution

This information will be included in a future release of the Intel® Stratix® 10 High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide.