Error(13381): Verilog HDL error at alt_vip_cps_alg_core_packer.sv(169): part-select has negative or zero size, but must use one or more bits

Description

Due to a problem with the Arria® 10 Color Plane Sequencer II IP core, you may see the above error in Quartus® Prime Pro software version 16.1 when compling the IP with a parameterization that uses more than one pixel in parallel.

Resolution

This problem has been fixed starting in software version 16.1.1 of the Quartus Prime Pro software.