Chainin and Chainout Ports in Arria 10 Native Fixed Point DSP IP Core Not Supported for m18x18_full Operation Mode.
Description When the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, the chainin and chainout ports are visible to users. However, these ports are disabled internally in m18x18_full operation mode. If you connect the chainin and chainout ports when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode, there will be no data transfer in and out to the DSP core. Resolution Leave the chainin and chainout ports unconnected when the Arria 10 Native Fixed Point DSP IP is configured to m18x18_full operation mode. This issue will be fixed in a future version of the Quartus II software.Why does MegaWizard report the multiplier output register option is no longer available when I upgrade my multiplier to Quartus 13.1?
Description The multiplier output register option is not available on 28nm ("V" series) devices. Resolution To resolve the error, disable the multiplier output register option and regenerate the core. If you wish to preserve the original latency introduced by the register, use the Pipelining tab to add a pipeline register with 1 clock latency. If an output register is desired, this can only be done for the adder output, on the Extra Modes tab.java.lang.UnsatisfiedLinkError: C:\altera\14.1\quartus\bin64\sld_utiljni.dll:
Description You may see this error when you change devices using the device icon in your DSP Builder design. The Quartus II software v14.1 needs Microsoft Visual C 2013; DSP Builder v14.1 needs Microsoft Visual C 2012. This problem affects DSP Builder v14.1 on Windows and users who install Altera Complete Design suite without administrator rights on PCs that don't already have Microsoft Visual C 2013. Resolution To work around this problem, install Microsoft Visual C 2013 from http://www.microsoft.com/en-gb/download/details.aspx?id=40784 This problem is scheduled to be fixed in a future version of DSP BuilderWarning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.
Description You may get this warning when simulating some DSP Builder® designs under Modelsim®. These warning messages do not have any effect on your simulation results, and can be ignored. Resolution These warnings (and all others like them) can be suppressed by either of two methods: Suppress via Modelsim GUI: Open the Simulation dialog box (Options menu). Set the option Suppress Warnings from Synopsys Packages to On. Click OK. Search for the *_atb.do file in your project directories, look for the comment "Disable some warnings ...", and comment out a later line as follows: # Disable some warnings that occur at the very start of simulation quietly set StdArithNoWarnings 1 run 0ns # quietly set StdArithNoWarnings 0 run -all Related Articles ASSERT/WARNING from package ieee.STD_LOGIC_ARITH, Built-in function result set to 'X' due to a ('U', 'X', 'W', 'Z', '-') in an operand / Built-in function CONV_INTEGER/TO_INTEGER argument too large Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0! (ModelSim, VHDL Output File (.vho))Why does Matlab crash with DSP Builder version 12.0 SP1?
Description Due to a problem in the installer for the Quartus® II software version 12.0 SP1, Matlab may crash with an error message similar to: AppName: matlab.exe AppVer: 7.13.0.0 ModName: msvcr90.dll ModVer: 9.0.30729.6161 Offset: 0006ccd5 Resolution A patch is available to fix this problem for the Quartus II software version 12.0 SP1. See the related solution below titled Why do my IP functions not reflect updates for the Quartus II software version 12.0 SP1? to download and install this patch. This problem is fixed beginning with the Quartus II software version 12.0 SP2. Related Articles Why do my IP functions not reflect updates for the Quartus II software version 12.0 SP1? Why does Matlab crash when I try to generate a design using Altera’s DSP Builder blockset?Does the Clocked Video Output (CVO) IP core support SDI 720p24 format?
Description The Altera® Clocked Video Output (CVO) IP core does not support the SDI 720p24 format. This is because the 4125 total horizontal lines of the SDI 720p24 format exceeds the 4096 maximum horizontal lines supported by the CVO. Resolution There is no plan to update the CVO IP core to support the SDI 720p24 format. However, this format will be supported in the Clocked Video Output II (CVO II) IP core in a future release of the Quartus® software.Why do I get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder?
Description You will get a VHDL Use Clause error in Quartus II when compiling a VHDL file generated by DSP Builder if you have not added the appropriate DSP Builder library files to your Quartus II project. These library files should already be added to the project for you if you run Quartus II from within SignalCompiler or if you use the Quartus II tcl script generated by DSP Builder. However, if you are running the Quartus II compile outside of SignalCompiler and are not using the Quartus II tcl script, you will need to set these library files up manually. The text of the error will look similar to: Error: VHDL Use Clause error at <filename>.vhd: design library does not contain primary unit dspbuilder block Error: Ignored construct <entity name> at <filename>.vhd because of previous errors To compile DSP Builder generated VHDL files in Quartus II, you must have the path to the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files specified in your Quartus II project. These files are located in the <DSP Builder install directory>\altlib directory. To add these files, select Add/Remove Files in Project... under the Project menu in Quartus II. Browse to the <DSP Builder install directory>\altlib directory and select the DSPBUILDERPACK.vhd and DSPBUILDER.vhd files and click OK to add the files. The compilation order of the files is important. DSPBUILDERPACK.vhd must be compiled before DSPBUILDER.vhd. Once you have included the files, rerun your Quartus II compile.Error: sdfse: couldn't load file "../quartus/dspba/backend/linux64/libdspip_recipes.so": /lib64/libc.so.6: version `GLIBC_2.14' not found
Description In the Intel® Quartus® Prime Pro Edition Software version 21.1 and later, you may see this error in Unified FFT Intel® FPGA IPs GUI messages when your OS is not supported. Resolution You need to use at least CentOS* 7.0 or SLES* 12. You can check more information on the supported OS at the below link. https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/os-support.htmlWhy does the Quartus® Prime Pro Edition software fitter allow the use of more Digital Signal Processing (DSP) blocks than a virtual part should provide?
Description Due to a problem in the Quartus® Prime Pro software version 18.1, when targeting Stratix® 10 devices, the device selector may report a different number of DSP blocks available for your device. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 19.1Unsupported Ports in Arria 10 Native Fixed Point DSP IP Core for m18x18_full and m27x27 Operation Modes
Description When you configure the Arria 10 Native Fixed Point DSP IP to m27x27 or m18x18_full operation mode, the following ports are not supported but visible to users: Operation mode: m18x18_full Unsupported ports: ACCUMULATE, LOADCONST, SUB and NEGATE ports Operation mode: m27x27 Unsupported ports: SUB port If you assert or deassert the ACCUMULATE, LOADCONST, SUB, and NEGATE ports in m18x18_full operation mode, the DSP core does not perform any operations enabled by these ports. If you assert or deassert the SUB port when using the Arria 10 Native Fixed Point DSP IP in m27x27 operation mode, the DSP core does not perform any arithmetic operation (addition or subtraction). Resolution Leave the ACCUMULATE, LOADCONST, SUB, and NEGATE ports unconnected when using the Arria 10 Native Fixed Point DSP IP in m27x27 and m18x18_full operation modes. This issue will be fixed in a future version of the Quartus II software.