Does the Agilex™ 5/3 FPGA HPS EMIF support the External Memory Interface Debug Toolkit?

Description

The HPS EMIF controller does support the External Memory Interface Debug Toolkit.  Using the following steps, create a design that instantiates the FPGA memory controller using the parameters for the HPS memory interface, and route it to the same I/O that the HPS EMIF uses.

 

Related Information

12.5. Debugging with the External Memory Interface Debug Toolkit

 

1. Select the HPS EMIF IP within the Platform Designer project.

2. Click Dive Into Packaged Subsystem in the External Memory Interfaces for HPS IP window.

3. In the new window, single-click on the EMIF IP inside the packaged IP window to view the Memory Device parameters on the right side, then click Generate Example Design.

4. Select the directory for the compile design:

5. The example design will be created.

NOTE:  If the HPS-EMIF is composed of 2 fabric-EMIFs, then the generated example design will only contain 1 fabric-EMIF.
 

NOTE:  The Use Debug Toolkit option will be turned on in the generated example design.

6. Save and exit the Dive Into Packaged Subsystem window.

Resolution

The support will begin in a future release of the Quartus® Prime Pro Edition Software.