Certain Reference Clock Frequencies Cause the Compilation of the Arria® 10 and Cyclone® 10 GX fPLL IP to Fail

Description

Compilation of the Arria® 10 and Cyclone® 10 fPLL IP may fail during the Fitter stage under the following circumstances:

• The IP is in Core or Cascade Source mode and the reference clock frequency is in the range of 49 MHz < Fref < 51.5 MHz.
• The IP is in Transceiver mode and the reference clock frequency is in the range of 50.0 MHz ≤ Fref < 51.5 MHz.

This issue affects both the Quartus® Prime Standard Edition software and the Quartus Prime Pro Edition software.

Resolution

Select the fPLL IP reference clock frequency that does not fall within the specified ranges.