Honored ContributorHi all,
What does the rClk[1..0] do in the system? the rClk[1] value is not used in the DE2_D5M demos but the register is added by 1 every clock cycle. The rClk[0] is then inverted from 0 to 1 every clock cycle, what is the use of this? Regards,
Honored ContributorA text search reveals, that rClk[0] is used in the design. rClk[1] isn't, simply ignore it, Quartus integrated synthesis will do, too.
Honored ContributorThanks, I see. But why does the design need to add 1 bit to the register? It just inverts the high signal to low.
Honored ContributorYes. The gate level logic is the same.
As written, you have the option to generate a lower speed clock by connecting the output to rClk[1].Honored ContributorOkay, thank you very much :)
