Pixel Buffer DMA Controller (altera_up_avalon_video_pixel_buffer_dma) generates Verilog HDL with syntax error

For example, when "Default Buffer Start Address" and "Default Back Buffer Start Address" is set as 0xFF010000, generated Verilog file contains following lines:

parameter DEFAULT_BUFFER_ADDRESS		= 32'd-16711680;
parameter DEFAULT_BACK_BUF_ADDRESS	= 32'd-16711680;

which causes the following errors:

Error (10170): Verilog HDL syntax error at core_video_pixel_buffer_dma.v(68) near text: "-". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10170): Verilog HDL syntax error at core_video_pixel_buffer_dma.v(69) near text: "-". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error (10112): Ignored design unit "core_video_pixel_buffer_dma" at core_video_pixel_buffer_dma.v(29) due to previous errors

Version: Quartus Prime Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition