Forum Discussion
BLee15
Occasional Contributor
Occasional ContributorPixel Buffer DMA Controller (altera_up_avalon_video_pixel_buffer_dma) generates Verilog HDL with syntax error
For example, when "Default Buffer Start Address" and "Default Back Buffer Start Address" is set as 0xFF010000, generated Verilog file contains following lines: parameter DEFAULT_BUFFER_ADDRESS = 3...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
This looks like if the MSB bit is "1", it represents a negative value, and somehow it added a "-" in the Verilog file and which is incorrect.
To prevent this problem, one of the workarounds is don't set the MSB bit (32nd bit) to "1". For example, 0x7f010000.
Regards -SK
BLee15I applied this workaround and it works as expected.
Nevertheless, please consider this as bug and fix code generator script.
