ModelSim Error - Undefined Variables and Global Declarations are Illegal in Verilog 2001 Syntax

Hello!

So I have defined two parameters, "START_ADDR" and "END_ADDR" in a verilog header file, called "audioparams.vh":

`ifndef AUDIO_PARAMS
`define AUDIO_PARAMS

parameter START_ADDR = 32'h0000AF30;
parameter END_ADDR = 32'h000700A0;

`endif

And I have included this header file in another Verilog file (called, Memory_Controller.v) in order to access these parameters from this Verilog file.

(An overview of what I have in Memory_Controller.v):

`include "audioparams.vh"

module Memory_Controller(
	input sysclock,
	input read_enable,
	//input [32:0] read_address,
	//input [7:0] input_data, 
	output reg [7:0] output_data,
	output reg reading_on,
	output reg reading_finished,
	input sysreset
);


//internal register holding current address
reg [31:0] present_address = START_ADDR;
wire [7:0] output_wire;
reg donereading = 1'b0;

And note that in Memory_Controller.v, I have included the audioparams.vh file. The project compiles without error on Quartus. However, when I attempt to run this TCL script on Modelsim:

#set the working directory, where all compiled Verilog goes
vlib work

#compile all verilog modules in top level module, to working directory
vlog Memory_Controller.v 

# load simulation using Memory_Controller as top level simulation module
vsim Memory_Controller audioparams.vh M10K_Memory.v 

# log all signals and add some signals to waveform window
log {/*}

# add wave {/*} would add all items in top level simulation module
add wave {/*}

# create clock
force {sysclock} 0 0ns, 1 {5 ns} -r 10ns 
#changes from 0 to 1 every 5 ns --> repeats every 10 ns

#turn on read enable --> read out audio samples
force {read_enable} 1;
run 500ns

(Where Memory_Controller.v is the top level module in the project)

When I attempt to run the TCL script above to generate a ModelSim simulation, I get these errors:

I am wondering why the terminal thinks that START_ADDR and END_ADDR are undefined variables even though the parameters are imported into this verilog file. I was also wondering if perhaps, only the top level module (i.e. Memory_Controller.v) is being compiled, instead of all the files in the project?

I am very lost and was wondering if I have made a dumb mistake somewhere that I did not notice LOL.

I appreciate your support, and please go easy on me. I am fairly new to ModelSim