Forum Discussion

jnspk's avatar
jnspk
Icon for New Contributor rankNew Contributor
1 year ago

ModelSim Error - Undefined Variables and Global Declarations are Illegal in Verilog 2001 Syntax

Hello! So I have defined two parameters, "START_ADDR" and "END_ADDR" in a verilog header file, called "audioparams.vh": `ifndef AUDIO_PARAMS `define AUDIO_PARAMS parameter START_ADDR = 32'h0000A...
University Program
HubertG's avatar
HubertG
Icon for Contributor rankContributor
1 year ago

We sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum case, did not reach us as intended. As a result, we have a backlog of cases that we are currently working through.

Please be assured that we are doing everything we can to resolve this as quickly as possible. This will take some time, and we appreciate your patience and understanding during this period of time. Your case will be attended by AE soonest possible.

Thank you again for your patience and understanding, and we are committed to provide you with the best possible support.