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jnspk's avatar
jnspk
Icon for New Contributor rankNew Contributor
2 years ago

ModelSim Error - Undefined Variables and Global Declarations are Illegal in Verilog 2001 Syntax

Hello! So I have defined two parameters, "START_ADDR" and "END_ADDR" in a verilog header file, called "audioparams.vh": `ifndef AUDIO_PARAMS `define AUDIO_PARAMS parameter START_ADDR = 32'h0000A...
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HubertG's avatar
HubertG
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1 year ago

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