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jnspk's avatar
jnspk
Icon for New Contributor rankNew Contributor
1 year ago

ModelSim Error - Undefined Variables and Global Declarations are Illegal in Verilog 2001 Syntax

Hello! So I have defined two parameters, "START_ADDR" and "END_ADDR" in a verilog header file, called "audioparams.vh": `ifndef AUDIO_PARAMS `define AUDIO_PARAMS parameter START_ADDR = 32'h0000A...
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FvM's avatar
FvM
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1 year ago

Hi,
you quoted the relevant error message in question title "no global parameters in Verilog". Seeing this error, why do you wonder about follow-ups? You can select SystemVerilog syntax for the respective modules, or use defined macros instead of parameters. Quartus apparently doesn't distinguish different Verilog revisions so strictly, or did you globally enable SV syntax in Quartus?