LVDS-Rx IP (DE10 SoC-Cyclone V) interfacing with external ADC : Error in compilation & clock routing

We're using a ALTERA Cyclone V DE10-SoC board and need to interface FPGA “altlvds_rx” IP with an external ADC's LVDS outputs (data, high speed clock, low speed clock).
We have tried directly connecting the FPGA pins (LVDS pair) to the “altlvds_rx” IP (Pin: “rx_in”, “rx_inclock”, “rx_enable”) for this purpose.

Issues:
1. When I instantiate “altlvds_rx” with Data and clock pins (Pin: “rx_in”, “rx_inclock”, “rx_enable”)
as the top module pins, and tried to compile, In Analysis & Synthesis step it showed:
• “WRITECLK” and “LOADEN” not properly connected.

Request:
• How can we correctly interface external ADC’s LVDS signals (data, high speed clock, low speed clock) to “altlvds_rx” via FPGA pins ?
• Any peripheral IP should be connected between Top pins (FPGA LVDS pair) and “altlvds_rx” pins (“rx_inclock”, “rx_enable”) to get rid of compilation error and also have successful routing ?
• Example designs or suggestions to resolve these errors and successfully interface FPGA “altlvds_rx” IP with external LVDS ADC outputs ?
Any guidance would be greatly appreciated.