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santosh2uu2's avatar
santosh2uu2
Icon for New Contributor rankNew Contributor
6 months ago

LVDS-Rx IP (DE10 SoC-Cyclone V) interfacing with external ADC : Error in compilation & clock routing

We're using a ALTERA Cyclone V DE10-SoC board and need to interface FPGA “altlvds_rx” IP with an external ADC's LVDS outputs (data, high speed clock, low speed clock). We have tried directly connect...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
6 months ago
Hi,
generally, it would be helpful to get a complete problem specification:
- Quartus version
- SERDES configuration details
- intended RX clocking method

You have apparently set SERDES RX module to external PLL operation without connecting a PLL (won't be possible for a top level module). That doesn't make much sense because you most likely don't have fast and slow clocks (inclock and rx_enable) with appropriate timing.