Forum Discussion
santosh2uu2
New Contributor
New ContributorLVDS-Rx IP (DE10 SoC-Cyclone V) interfacing with external ADC : Error in compilation & clock routing
We're using a ALTERA Cyclone V DE10-SoC board and need to interface FPGA “altlvds_rx” IP with an external ADC's LVDS outputs (data, high speed clock, low speed clock). We have tried directly connect...
WZ2
Frequent Contributor
Frequent ContributorHi there,
- For this IP, the example design can typically be generated by selecting the "Generate Example Design" option in the IP parameter editor. You may try generating it under a Cyclone 10 or Arria 10 device — the IP itself is the same across these devices.
- Regarding the three pins you asked about, their connection method largely depends on your specific IP configuration. Based on your question, I assume you're trying to use an external PLL? Without knowing the exact IP settings, I can only make some general assumptions. The Clock input should be connected to a pin that supports clk_in functionality — please refer to the device's pin list to ensure compatibility.
Let me know if you can share more about your configuration — I’d be happy to provide more specific suggestions.
Best regards,
WZ
