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BlackByte10xy's avatar
BlackByte10xy
Icon for New Contributor rankNew Contributor
5 years ago

I have a question about verilog!

Hello,

I have a compile error in quartus II when I try to do a counter with asynchronous reset. The error comes from the sensitivity list of the always process. The part of the code is as follows:

/----------

always @ ( posedge iCLK, iRST_n )
begin
if ( iRST_n == 0 )

oCOUNT = 0;

else

...

/----------

The error that the quartus II gives me is the following:

Error (10122): Verilog HDL Event Control error at contador.v(54): mixed single- and double-edge expressions are not supported

/----------

The question is: How can I implement an asynchronous reset on a counter in verilog?

Thanks

2 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    You may checkout the webpage below to help you on the Verilog design.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/desig...

    Other than that, our Quartus tool has a variety of Verilog design template in which you can just pop it into your project and use it right away.

    Example:
    In the new created Verilog .v file, right-click on the black space to opens the context menu, scroll to Insert Template, a window Insert Template will pop up, choose Verilog HDL > Full Designs > Counters > Binary Counter.

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.