Generate Triangular Wave Table

Hi,

Things are done in different ways. For a triangular wave I will use a counter.

It is easy but there are some subtleties.

Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from

(-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement)

The following untested code gives you the idea of getting 100 samples per period:

The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples)

signal count : signed(7 downto 0);

------

process(reset,clk) -- assuming clk = 6KHz

if reset= '1' then

count <= -125;

updown <= '0';

elsif rising_edge(clk) then

if updown = '0' then

if count < 125

count <= count + 5;

end if;

if count = 120 then

updown <= '1';

end if;

else -- if updown = '1' then

if count >-125

count <= count - 5;

end if;

if count = -120 then

updown <= '0';

end if;

end if;

end if;

end process;

output <= std_logic_vector(count);

--- Quote Start ---

Hi,

Things are done in different ways. For a triangular wave I will use a counter.

It is easy but there are some subtleties.

Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from

(-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement)

The following untested code gives you the idea of getting 100 samples per period:

The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples)

signal count : signed(7 downto 0);

------

process(reset,clk) -- assuming clk = 6KHz

if reset= '1' then

count <= -125;

updown <= '0';

elsif rising_edge(clk) then

if updown = '0' then

if count < 125

count <= count + 5;

end if;

if count = 120 then

updown <= '1';

end if;

else -- if updown = '1' then

if count >-125

count <= count - 5;

end if;

if count = -120 then

updown <= '0';

end if;

end if;

end if;

end process;

output <= std_logic_vector(count);

--- Quote End ---

Hi !

I tried using this code but I'm getting errors with the minus sign in front of 125. How should it be placed on the code ?

Declare count as:

signal count: signed(7 downto 0);

--- Quote Start ---

Hi,

Things are done in different ways. For a triangular wave I will use a counter.

It is easy but there are some subtleties.

Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from

(-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement)

The following untested code gives you the idea of getting 100 samples per period:

The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples)

signal count : signed(7 downto 0);

------

process(reset,clk) -- assuming clk = 6KHz

if reset= '1' then

count <= -125;

updown <= '0';

elsif rising_edge(clk) then

if updown = '0' then

if count < 125

count <= count + 5;

end if;

if count = 120 then

updown <= '1';

end if;

else -- if updown = '1' then

if count >-125

count <= count - 5;

end if;

if count = -120 then

updown <= '0';

end if;

end if;

end if;

end process;

output <= std_logic_vector(count);

--- Quote End ---

Hi,

I've been trying to generate a triangular wave that can go up to 76, based on your example. The waveform goes up to 64, then goes down with negative values until a point then goes to 63 to count down properly. What could be the problem ?

P.S :See attached file

--- Quote Start ---

Hi,

Things are done in different ways. For a triangular wave I will use a counter.

It is easy but there are some subtleties.

Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from

(-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement)

The following untested code gives you the idea of getting 100 samples per period:

The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples)

signal count : signed(7 downto 0);

------

process(reset,clk) -- assuming clk = 6KHz

if reset= '1' then

count <= -125;

updown <= '0';

elsif rising_edge(clk) then

if updown = '0' then

if count < 125

count <= count + 5;

end if;

if count = 120 then

updown <= '1';

end if;

else -- if updown = '1' then

if count >-125

count <= count - 5;

end if;

if count = -120 then

updown <= '0';

end if;

end if;

end if;

end process;

output <= std_logic_vector(count);

--- Quote End ---

See my attached file. What could be the problem ?

Don't read too much into my syntax and especially >, < etc.

The purpose is to give the idea only.

A neat way is to have two states (s1,s2)

in s1 : count goes up and change state

in s2: count goes down and change state

--- Quote Start ---

Don't read too much into my syntax and especially >, < etc.

The purpose is to give the idea only.

A neat way is to have two states (s1,s2)

in s1 : count goes up and change state

in s2: count goes down and change state

--- Quote End ---

I've managed to fix that code and it can now produce a PWM by comparing it with a sine wave , using a look up table in VHDL, but now I was asked to produce a sine wave with a C code written for a Nios II core. I've actually written one, but using sin function. Would it be better if I write one with the look up table instead? And plz do you have a simple example for such a code?