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Hi,
Things are done in different ways. For a triangular wave I will use a counter.
It is easy but there are some subtleties.
Remember the period of your wave = Fs/60 where Fs is your clk frequency or enable frequency. To get things clean and without dc offset I can use Fs of 6KHz then the period = 100 so I can use an 8 bit counter that goes from
(-125 to 125) and back incrementing/decrementing by 5. (check that your ADC uses 2'Scomplement)
The following untested code gives you the idea of getting 100 samples per period:
The wave goes from -125 to 125 (51 samples) then 120 to -120 (49 samples)
signal count : signed(7 downto 0);
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process(reset,clk) -- assuming clk = 6KHz
if reset= '1' then
count <= -125;
updown <= '0';
elsif rising_edge(clk) then
if updown = '0' then
if count < 125
count <= count + 5;
end if;
if count = 120 then
updown <= '1';
end if;
else -- if updown = '1' then
if count >-125
count <= count - 5;
end if;
if count = -120 then
updown <= '0';
end if;
end if;
end if;
end process;
output <= std_logic_vector(count);
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See my attached file. What could be the problem ?
Honored Contributor
