De2-115 remove the default project

You are probably compiling your project into a .sof file and downloading it directly into the FPGA configuration RAM.

It will be active UNTIL you power cycle the board as the RAM configuration does not persist without power.

At power up the configuration EPROM will be read and loaded into the device (the boards are normally setup to do this).

So that is why if you power cycle the board the 'default' configuration stored in the config EPROM reappears.

What you need to do, besides compiling your project to a .sof file, is use the Quartus tool quartus_cpf to generate a config EPROM .jic

which you can then download to the EPROM.

For example I run:

quartus_cpf -c DESIGN.cof

where DESIGN.cof contains:

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
	<eprom_name>EPCS64</eprom_name>
	<flash_loader_device>EP4CE115</flash_loader_device>
	<output_filename>DESIGN.jic</output_filename>
	<n_pages>1</n_pages>
	<width>1</width>
	<mode>7</mode>
	<sof_data>
		<user_name>Page_0</user_name>
		<page_flags>1</page_flags>
		<bit0>
			<sof_filename>DESIGN.sof</sof_filename>
		</bit0>
	</sof_data>
	<version>4</version>
	<options>
		<map_file>1</map_file>
	</options>
</cof>

And you will want to add the Altera serial flash loader module into your top level module as well (assuming verilog here):

    // Altera Serial Flash Loader module

    // Allows external JTAG access to the serial config eeprom for programming

    sfl	sfl
	( .asdo_in		(1'b0),		// not used
	  .dclk_in		(1'b0),		// not used
	  .ncso_in		(1'b0),		// not used
	  .noe_in		(1'b0),		// always enabled
	  .asmi_access_granted	(1'b1),		// external JTAG access always
	  .asmi_access_request	(),		// not used
	  .data0_out		()		// not used
	  );

You ought to view this ...

https://www.intel.com/content/www/us/en/docs/programmable/683299/current/using-the-fpga-serial-flash-loader-ip-85096.html

Hi, after some search, I created the .jic file. However, in my programmer, when I started the progress, it failed. I think that it is downloading to the board because the LCD is removed ("welcome to the Altera DE2-115" is displayed), and the LEDs are off. Surprisingly, even now, if I plug in a speaker with a mic, the board plays sound.

Please find the attached photos. What am I missing?Also if i select file type .jic the only choice for configuration device is EPCQL1024.

Is it not possible to completely remove the default project when I power up the device?

If you look here:

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=4#contents

The link to the user manual is available as a PDF file.

On pages 12-13 section 2.3 it describes the behavior of the default program in EPROM provided on a new board.

The welcome message you indicate is written to the LCD. And the sound behavior you described is present.

So if you continue to see that message you are not overwriting the default program in EPROM.

I would suggest that you download the support CDROM from the TerAsic site and follow their examples.

Hello,

I’m glad that your question has been addressed, for now I will set this case to Close-Pending.

Regards,

Nazrul Naim