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Altera_Forum's avatar
Altera_Forum
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18 years ago

Building serial communication...

Hi,

I am using a FLEX10K UP2 board and want to do some image processing on it. I would like to build an 8-bit internal RAM for my FPGA in order for my design file to write data to the RAM and read data from my CPU. I have been advised to use the serial communication to achieve data interaction between my CPU and FPGA. Since I am a beginner here, my questions would be:

  • Any suggestion on creating internal RAM? By using and altsyncram and associate it to my design file?

  • If so, then how to establish a serial commucation between my CPU and then internal RAM? Is SOPC Builder useful here? In the mean time, I have done some reading on UART, RS232, parallel-in-serial-out register and serial-in-parallel-out register.

I really appreciate for any references related to above issues.

Thanks.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I don’t aware that the IP does not support Flex10k. Thanks for the correction.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I also nearly forgot, that there have been FPGA without SignalTap, Memory Content Editor and all these functions depending on virtual JTAG. I knew with Flex10k from a preceeding topic.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    Thanks for all the advice. I now studying the design reference as provided in Opencores.org.

    But how do SignalTap, Memory Content Editor and all these functions affect my UART design?

    Thanks!!!
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The said tools don't affect your design, cause they aren't available with Flex10K. Would be interesting tools otherwise.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    If it helps I can send you my own UART IPcore. I wrote it for one of my projects. It requires 50 MHz clock signal and has user-set baudrate from 150 to 38400 bps. Write me an e-mail if you will need it (zaquadnik@gmail.com).