4-bits universal binary counter

Write a VHDL code to design a universal binary counter

 Assign the I/O ports to the boards I/O pins as follows: Design I/O port Board I/O pin
Clock (clk)
CLK_50M
Enable (en)
V_SW(0)
Count up (up)
V_SW(1)
Clear (syn_clr)
V_BT(0)
load
V_BT(1)
Output (q)
G_LED (3 downto 0)
Input (d)
V_SW(5 downto 2)
 Synthesize the circuit and upload it to the FPGA prototyping board.
 Verify the operation of counter.
Hint: you will need to slow down the main clock frequency (50MHZ) to see the LEDs blinking pattern. Use cycle counter to control the counter operations.
Max Count = Max Frequency/Desired Frequency