Occasional ContributorHI,
Why do I see the mem pins in Quartus for the HPS? I'm coming from a Nios background, in Nios with Qsys I understand that it's all soft and the mapping to pins is defined as part of the Quartus IP..... but with the HPS is the SDRAM interface not defined "hard" with fixed pins..... and why does it show up in an export from Qsys module?
thanks, confused.
Regular ContributorHi,
Qsys provides a complete simulation model of the HPS memory interface controller, providing cycle-level accuracy, comparable to the simulation models for the FPGA memory interface.
"The simulation model supports only the skip-cal simulation mode; quick-cal and full-cal are not supported. An example design is not provided, however you can create a test design by adding the traffic generator component to your design using Qsys. Also, the HPS simulation model does not use external memory pins to connect to the DDR memory model; instead, the memory model is incorporated directly into the HPS SDRAM interface simulation modules. Simulation of the FPGA-to-SDRAM interfaces requires that you first bring the interfaces out of reset, otherwise transactions cannot occur."
You can refer here for more information:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_ip.pdf#page=297
Hopes this helps your confusion.
Regards.
Occasional ContributorThanks for the answer, so it is only to aid simulation and has no real affect on the programming of the FPGA at all?
Thanks once again
Regular ContributorYeap, it shouldn't affect the programming.
Regards.
