New Contributor
Frequent ContributorHi
Please let us know whether you are using a custom board
also in the socfpga.dtsi file which you are using whether a cell similar to this is present
rst: rstmgr@ffd05000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
altr,modrst-offset = <0x10>;
};
if yes what is the address mentioned in the cell , is it same like ffd05000 or some thing else.
Also having reserved bits in a register doesn't mean that you cannot read the register. It means that you cannot change those bits or use it for some custom functionality.
Regards
Anil
New ContributorHi Anil,
Before answering your question, one small update. We have SPL enabled and I moved my code in the very beginning of board_init_f:
@@ -306,6 +310,7 @@ void board_init_f(ulong dummy)
* First C code to run. Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
*/
+ reset_cause = readl(&reset_manager_base->status);
reg = readl(&sysmgr_regs->eccgrp_ocram);
if (reg & SYSMGR_ECC_OCRAM_SERR)
writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
@@ -316,6 +321,7 @@ void board_init_f(ulong dummy)And I am displaying it later when SPL partition index is printed.
Yes, the board is our design.
The cell in socfpga.dtsi is similar. Our missing "altr,modrst-offset = <0x10>;" and I added it just in case. The address is the same.
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -754,6 +754,7 @@
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
};I also added in some desperate move in our dtsi the next:
--- a/arch/arm/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5.dtsi
@@ -28,6 +28,10 @@
smplsel = <0>;
};
+ rstmgr@ffd05000 {
+ status = <0xffd05000>;
+ };
+But without success.
Cordially
Georgi
P.S. Do you know how to make warm reset from u-boot. I found one thread here before one year, and the person was complaining the same as me with not custom board. But at least he had warm reset bit read.
