New ContributorWhy can not my u boot configure DRAM? (external fpga config)
Dear all,
I have a question about the U-boot. Using the hardware board is designed by myself. The SoC is 10AS066N2.
The U-Boot runs perfectly when the fpga configured from u-boot from QSPI flash. I'm trying to configure fpga from external EPCQL.
- Checked external-fpga-config box on u-boot.
- Programmed the epcql with the JIC file that converted from sof file that rbf files origin.
- I checked the clock that drives the DDR clock pin.
Why is the CPU continuously resetting?
U-Boot 2014.10 (Oct 10 2019 - 14:33:00)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe3a6e8
DRAM : 0 Bytes
data abort
pc : [<ffe001cc>] lr : [<ffe0249d>]
sp : ffe3fff0 ip : 00000016 fp : 00000001
r10: ffd02078 r9 : ffe3aee8 r8 : ffe00000
r7 : ffe1d3d4 r6 : 00000000 r5 : 00000000 r4 : ffeff000
r3 : ffe3afaf r2 : ffe40000 r1 : ffe3d000 r0 : ffe3aee8
Flags: nzcv IRQs on FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
U-Boot 2014.10 (Oct 10 2019 - 14:33:00)
CPU : Altera SOCFPGA Arria 10 Platform
BOARD : Altera SOCFPGA Arria 10 Dev Kit
I2C: ready
DRAM: WARNING: Caches not enabled
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
emif_reset interrupt acknowledged
Error: Could Not Calibrate SDRAM
DDRCAL: Failed
INFO : Skip relocation as SDRAM is non secure memory
Reserving 2048 Bytes for IRQ stack at: ffe3a6e8
DRAM : 0 Bytes
data abort
pc : [<ffe001cc>] lr : [<ffe0249d>]
sp : ffe3fff0 ip : 00000016 fp : 00000001
r10: ffd02078 r9 : ffe3aee8 r8 : ffe00000
r7 : ffe1d3d4 r6 : 00000000 r5 : 00000000 r4 : ffeff000
r3 : ffe3afaf r2 : ffe40000 r1 : ffe3d000 r0 : ffe3aee8
Flags: nzcv IRQs on FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
