Forum Discussion
MCETIN
New Contributor
New ContributorWhy can not my u boot configure DRAM? (external fpga config)
Dear all, I have a question about the U-boot. Using the hardware board is designed by myself. The SoC is 10AS066N2. The U-Boot runs perfectly when the fpga configured from u-boot from QSPI flash. ...
MCETINNew Contributor
New ContributorHello, I solve the problem.
In my situation, DDR ref clock was discontinuous becaouse the programmable ddr ref clock IC has been programming while DDR calibration. I change the programmable IC with hard programmed IC and the problem is solved.
So you need to check all part of your DDR design.
