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MCETIN's avatar
MCETIN
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7 years ago

Why can not my u boot configure DRAM? (external fpga config)

Dear all, I have a question about the U-boot. Using the hardware board is designed by myself. The SoC is 10AS066N2. The U-Boot runs perfectly when the fpga configured from u-boot from QSPI flash. ...
MCETIN's avatar
MCETIN
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6 years ago

Hello, I solve the problem.

In my situation, DDR ref clock was discontinuous becaouse the programmable ddr ref clock IC has been programming while DDR calibration. I change the programmable IC with hard programmed IC and the problem is solved.

So you need to check all part of your DDR design.