Unable to Compile FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev E baremetal project in Eclipse on Windows 10 Machine.

Question

Hi,I downloaded the following project for Cyclone V SOC Development Kit:-FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev Eand programmed the FPGA using .sof file on my kit which is done successfully.However, when I try to compile the software project in eclipse on my Windows 10 machine, it gives the following error attached in the image file.Why is such error here? How do I remove this error?

mhada · Answer

I am unable to find cycloneV_hps_arm_a9_0.hWhere can it be found? Please inform.Also please let us know as to why this problem is coming?

eberlazare_i_intel · Answer

Hi,Can you rebuild the project by following the steps below from page 26 to page 29:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf#page=26

eberlazare_i_intel · Answer

Hi,Have you try rebuilding the project following the steps above?I did face the similar error when using a prebuilt project, thus I attempt to rebuild the project and it does removes the error.

Forum Discussion

Unable to Compile FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev E baremetal project in Eclipse on Windows 10 Machine.

3 Replies

Recent Discussions

Unique ID registers in Cyclone V

Audio interface with Agilex 5 A5ED065BB32AI4S

Operating system kernel-level FPGA bridge communication

Routing PL DDR to PS

Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel