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MHada
Occasional Contributor
Occasional ContributorUnable to Compile FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev E baremetal project in Eclipse on Windows 10 Machine.
Hi, I downloaded the following project for Cyclone V SOC Development Kit:- FPGA-to-HPS Bridge Design Example for CV SoC DevKit Rev E and programmed the FPGA using .sof file on my kit which is done...
EBERLAZARE_I_Intel
Regular Contributor
Regular ContributorHi,
Can you rebuild the project by following the steps below from page 26 to page 29:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf#page=26
