Stratix 10 SoC bare metal, no hps_isw_handoff generated
Greetings. I am trying utilize the Stratix 10 SoC HPS (bare metal for now) for the first time. I am using Quartus Prime Pro 19.2. So far, I have used the Platform Designer to instantiate a "Hard Processor System Intel Stratix 10 FPGA IP" and a very simple AXI-Lite GPIO module. I validated the design, generated HDL, and then Compiled the design in Quartus.
I am now trying to "import" whatever files the "Eclipse for DS-5" needs to develop software for this system. I imagine this will create some kind of BSP that will generate linker scripts and header files as appropriate for this specific design, and then I can develop my embedded software for the application.
I can't find a very good step-by-step instruction of doing this (I feel like there should be a tutorial just to go through the motions and get used to the mechanics, but I can't find it), but I have gathered bits and pieces from around the web: It looks like the flow is to use the bsp-editor tool available from "Embedded_Command_Shell.bat", and this asks to point to the "Preloader Settings Directory" which should contain hps.xml and emif.xml.
Everything I've found seems to indicate that Quartus should generate a folder called "hps_isw_handoff" which contains these files, but my project is not producing this.
Are there additional settings I need to enable to get this directory to be built? I noticed that my Quartus Prime Pro version is 19.2, but the latest SoC EDS available for download is only at 19.1. Do these versions need to align?