Stratix 10 SoC bare metal, no hps_isw_handoff generated

Hi,

Depending on the exact bootloader and SoC device family, the handoff can take various forms. For Intel Stratix 10 SoCs, the handoff information is part of the FPGA configuration bitstream.

Based on my knowledge, a "hps_isw_handoff" folder will be created when you have compiled your project successfully in Quartus when using Cyclone V Soc or Arria 10 SoC boards. For Startix 10 SoC the handoff information is located in the "output_files" directory of your project folder.

You can find the demonstration of the steps when the handoff information is created below in the "Compiling Hardware Design" tab: https://rocketboards.org/foswiki/Documentation/S10GSRDCompilingHardwareDesign180

We also have this documented in our website available here:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-guidance/soc-bootloader.html

From above link, you can direct to the "Hardware Handoff" section on the left side where you can find more information regarding the handoff information.

I recommend you check https://rocketboards.org/foswiki/Main/GettingStarted to learn more on other topics as well.

Let me know if you need more help.

Thanks.