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Sajeev_antony's avatar
Sajeev_antony
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1 day ago

Stratix 10 HPS 8GB SODIMM shared memory for HPS and FPGA

We have custom board with stratix 10 FPGA. the HPS boots from 8GB eMMC and teh linux runs of 2GB soldered DDR4. We also have a 8GB DDR4 SODIMM which we plan to use as a shared memory between the HPS ...
embedded peripheral
Hps Arch
AnnaK_Altera's avatar
AnnaK_Altera
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1 hour ago

Hi Sajeev_antony​,

Typically, you would let Platform Designer generate the arbitration logic for EMIF with multiple Avalon-MM/AXI masters, or design a custom logic if the generated one doesn't match your needs - we don't offer a Multi-Port Front-End wrapper for Stratix 10 EMIF. You can then connect the HPS h2f bridge to the same conduit as the other masters.

The HPS-to-FPGA bridge provides access to 4GB of address space: https://docs.altera.com/r/docs/683222/25.3.1/stratix-10-hard-processor-system-technical-reference-manual/hps-to-fpga-bridge
For access to the full 8GB SODIMM, you would need an Address Span Extender IP to access the entire 8GB: https://docs.altera.com/r/docs/683364/18.1/intel-quartus-prime-standard-edition-user-guide-platform-designer/address-span-extender

You should consider the bandwidth and latency needs for each master that needs access to the EMIF, and optimize accordingly.

Regards,

AK