Forum Discussion
HPark14
Occasional Contributor
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Hello guys,
I've resolved this issue. Thank you for your support.
I created a r_out register and exported it to the top-level output
after that Quartus compilation succeeded.
HPark14Occasional Contributor
Occasional ContributorWhy does Quartus optimize?
RDATA is not connected.
tehjingy_Altera
Regular Contributor
Regular ContributorHi KoenVe
Unfortunately this is required. The expectation from the Quartus is to always have something connected to each F2SDRAM port (write and read).
