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HPark14
Occasional Contributor
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys, We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
HPark14Occasional Contributor
Occasional ContributorThank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.
Thanks~
Archer_AlteraOccasional Contributor
Occasional ContributorHi HPark14,
I suggest you to add one AXI bridge component between f2sdram interface of HPS and AXI master interface of your own module. Then this error will disappear. You may see other error but they may be solved easier.
Hope this is helpful.
Archer_Altera
