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HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
3 months ago
Solved

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
Hps Arch
  • HPark14's avatar
    HPark14
    2 months ago

    Hello guys,

     I've resolved this issue. Thank you for your support.

    I created a r_out register and exported it to the top-level output 

    after that Quartus compilation succeeded.

HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Thank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.

Thanks~

Archer_Altera's avatar
Archer_Altera
Icon for Occasional Contributor rankOccasional Contributor
3 months ago

Hi HPark14​,

I suggest you to add one AXI bridge component between f2sdram interface of HPS and AXI master interface of your own module. Then this error will disappear. You may see other error but they may be solved easier.

Hope this is helpful.

Archer_Altera