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HPark14's avatar
HPark14
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13 days ago

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
Hps Arch
HPark14's avatar
HPark14
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12 days ago

Why does Quartus optimize?

RDATA is not connected.

tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
8 days ago

Hi HPark14 

 

I would suggest to take a look at the way the termination of f2sdram signal in the following file in the example:

 

f2sdram_terminator_reg_256_hw.tcl

f2sdram_terminator_64_hw.tcl