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Contributor

3 months ago

Cyclone V HPS bus - FPGA-to-SDRAM

Dear Intel, and all, Brian here and there is a very puzzling documenting on: https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html Based on the 256 bi...

BoonBengT_Altera

Moderator

2 months ago

Hi @BrianSune_Froum,

After some alignment internally, there seems to be no further clarification, but more toward the way the documentation are written. Noted on the inputs and will bring this back internally.

With that please do let us now if there is further doubts in regards to this matter.

Best Wishes

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Cyclone V HPS bus - FPGA-to-SDRAM

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