Forum Discussion

서박사's avatar
서박사
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

ALTERA function fails after execution at C program

Hello, I'm using DE1-SoC with lubuntu 16.04. I'm trying to make a C program to access the HPS resources such as LED, GPIO, etc. """ I was using the kernel from Terasic, and the C program wi...
  • IntelSupport's avatar
    IntelSupport
    4 years ago

    Hello서박사,

    I’m glad that your problem has been fixed.

    So I will close this thread if no further questions from you.

    Best regards,

    Yoshiaki Saito


YoshiakiS_Altera's avatar
YoshiakiS_Altera
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello Hi서박사,

Basically, you should build DTB from DTS in same Kernel tree.

So could you please try the latest Linux Ubuntu Desktop(2016-12-28) in new SD-CARD again just in case?

Lastly, Bus size of LED is 32 bit as below. You should use md.l or md command to access the port instead of md.w.

2.3.1 Red LED Parallel Port

https://ftp.intel.com/Public/Pub/fpgaup/pub/Intel_Material/18.1/Computer_Systems/DE1-SoC/DE1-SoC_Computer_NiosII.pdf#page=4

Best regards,

Yoshiaki Saito

서박사's avatar
서박사
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hello Yoshiaki,

Thank you for the answer.

Using the latest Linux Ubuntu Desktop (v1.0, 2016-12-28) from Terasic resource center, U-boot fails with the following logs.

Booting log:

U-Boot SPL 2013.01.01 (Oct 12 2016 - 10:38:03)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 925 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3613 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
ALTERA DWMMC: 0


U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)

CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1 GiB
MMC: ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address

Hit any key to stop autoboot: 0
reading u-boot.scr
200 bytes read in 4 ms (48.8 KiB/s)
## Executing script at 02000000
reading soc_system.rbf
7007184 bytes read in 327 ms (20.4 MiB/s)
## Starting application at 0x3FF795A4 ...
## Application terminated, rc = 0x0
reading zImage
5538512 bytes read in 257 ms (20.6 MiB/s)
reading socfpga.dtb
31245 bytes read in 6 ms (5 MiB/s)
## Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x00000100
reserving fdt memory region: addr=0 size=1000
Loading Device Tree to 03ff5000, end 03fffa0c ... OK

Starting kernel ...

In addition, 32bit read of the register also fails with the logs as follows:

logs:

U-Boot SPL 2013.01.01 (Oct 12 2016 - 10:38:03)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 925 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3613 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
ALTERA DWMMC: 0


U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)

CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1 GiB
MMC: ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC address

Hit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 # fatload mmc 0:1 $fpgadata soc_system.rbf;
reading soc_system.rbf
7007204 bytes read in 361 ms (18.5 MiB/s)
SOCFPGA_CYCLONE5 # fpga load 0 $fpgadata $filesize;
SOCFPGA_CYCLONE5 # run bridge_enable_handoff;
## Starting application at 0x3FF795A4 ...
## Application terminated, rc = 0x0
SOCFPGA_CYCLONE5 # run mmcload;
reading zImage
5676720 bytes read in 286 ms (18.9 MiB/s)
reading socfpga.dtb
31245 bytes read in 8 ms (3.7 MiB/s)
SOCFPGA_CYCLONE5 # md FFD0501C 1
ffd0501c: 00000000 ....
SOCFPGA_CYCLONE5 # md FF200000 1
ff200000:

(freezes)

I really appreciate your time and effort on this thread.

Thank you!

  • 서박사's avatar
    서박사
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    I think I found the error source and fixed it.

    The main reason was the malfunction of the clock source at the FPGA.

    In the attached .qsys file, almost all FPGA components are based on the output clock of the PLL, which reference clock is provided by PIN_AF14.

    However, I found that this clock source is not working.

    I revised the system configuration to take a clock source from PIN_K14, not from PIN_AF14.

    Thus, everything works well.

    The logs are as follows:

    root@DE1_SoC:~> ./memtool FFD0501C 1
    Reading 0x1 count starting at address 0xFFD0501C

    0xFFD0501C: 00000000

    root@DE1_SoC:~> ./memtool FF200000 1
    Reading 0x1 count starting at address 0xFF200000

    0xFF200000: 000003FF (This result is intended)

    I'm sorry for making this thread to be too long since I'm not familiar with the embedded system, including FPGA.

    And again, I really appreciate your time and effort on this issue.

    Thank you!!