Forum Discussion
ALTERA function fails after execution at C program
- 4 years ago
Hello서박사,
I’m glad that your problem has been fixed.
So I will close this thread if no further questions from you.
Best regards,
Yoshiaki Saito
Hello Yoshiaki,
Thank you for your prompt response and the suggestion!
I've tried to use memtool from the above link but failed to cross-compile it since my cross-compile environment doesn't have autoconfigure
So I used another source code from the site below to compile memtool:
https://gist.github.com/mike0/2910170
Unfortunately, the read/write operation from/to certain registers (especially, FPGA-related registers) fail.
TChat is, the terminal does not respond to any commands like case the above.
I tried following commands (1 word = 32 bit):
#1
memtool FF001000 1 (read 1 word from 0xFF001000)
Reading 0x1 count starting at address 0xFF001000
0xFF001000: 00000000
#2
memtool FF200000 2 (read 2 words from 0xFF200000, while 0xFF200000 means LEDR)
Reading 0x3 count starting at address 0xFF000000
(freezes)
#3
memtool FF200020=16 (write 32bit word 16 to 0xFF200020, while 0xFF200020 means 7-segment displays register)
Writing 32-bit value 0x16 to address 0xFF200020
(freezes)
#4
memtool FFFEC600 3 (read 3 words from 0xFFFEC600, while 0xFFFEC600 means ARM A9 Private Timer)
Reading 0x3 count starting at address 0xFFFEC600
0xFFFEC600: 00234934 00165135 00000005
#5
memtool FFFEC600 3 (read 3 words again from 0xFFFEC600)
Reading 0x3 count starting at address 0xFFFEC600
0xFFFEC600: 00234934 00138EB5 00000005
The addresses of the registers are based on DE1-SoC_Computer_ARM.pdf
From the above result, should I suppose the FPGA hardware malfunction?
+ More logs using memtool
#6
memtool FFD0501C 3 (read 3 words from 0xFFD0501C, while 0xFFD0501C means FPGA Bridge)
Reading 0x3 count starting at address 0xFFD0501C
[ 68.718423] 8<--- cut here ---
[ 68.725699] Unhandled fault: external abort on non-linefetch (0x1018) at 0xb6f0c024
[ 68.733491] pgd = 64d55855
[ 68.736193] [b6f0c024] *pgd=3ffb8831
Bus error (core dumped)
#7
memtool C0000000 1 (read 1 words from 0xC0000000, while 0xC0000000 means SDRAM)
Reading 0x1 count starting at address 0xC0000000
(freezes)
- YoshiakiS_Altera4 years ago
Occasional Contributor
Hello 서박사,
Thank you for sharing the logs with us.
First of all, you need to confirm Cyclone V SoC register map below.
Cyclone V HPS Register Address Map and Definitions
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1418687413697.html
In case of #6, FFD0501C and FFD05020 are valid. But FFD05024 is undefined.
If you access undefined area, AXI bus might response SLVERR or DECERR.
The error will cause Bus Error.
In case of the freezes, could you please try these addresses using 'md' command on U-boot?
If you encounter an error, HPS2FPGA and Lightweight HPS2FPGA bridges might be disabled.
Please check brgmodrst register (0xffd0501c).
The bridges should be enabled on U-Boot.
Best regards,
Yoshiaki Saito
- 서박사4 years ago
Occasional Contributor
Hello Yoshiaki,
Thank you again for your suggestion.
I've checked the register at the address 0xffd0501c and at the address FF200000 and got the result as follows:
Booting log
U-Boot 2013.01.01 (Oct 12 2016 - 10:40:34)
CPU : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C: ready
DRAM: 1 GiB
MMC: ALTERA DWMMC: 0
*** Warning - bad CRC, using default environmentIn: serial
Out: serial
Err: serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net: mii0
Warning: failed to set MAC addressHit any key to stop autoboot: 0
SOCFPGA_CYCLONE5 # md.w FFD05020 2
ffd05020: 0000 0000 ....
SOCFPGA_CYCLONE5 # md.w FF200000 1
ff200000:(freeze)
As far as I know, if the last 3 bit is low (0), the bridges are enabled.
I've also checked that if FPGA itself is not working properly through operating the FPGA in active-serial mode, but I found that the operation of the FPGA is not the issue.
Please let me know if there is any other method to debug this error.
I appreciate your time and effort. Thank you!
- 서박사4 years ago
Occasional Contributor
For your information,
In addition, md command failure log is different between the following u-boot command:
command
run bridge_enable_handoff;
log
## Starting application at 0x3FF795A4 ...
## Application terminated, rc = 0x0before the command, md fails as follows:
command
md.b FF200000 1
log
ff200000:data abort
MAYBE you should read doc/README.arm-unaligned-accesses
pc : [<3ff95052>] lr : [<3ff95027>]
sp : 3ff355b0 ip : 0000001c fp : 00000002
r10: ff200000 r9 : ff200000 r8 : 3ff35f60
r7 : 00000000 r6 : 00000001 r5 : 00000001 r4 : 00000001
r3 : ff200000 r2 : c0000000 r1 : 3ff355bc r0 : 00000009
Flags: Nzcv IRQs on FIQs off Mode SVC_32
Resetting CPU ...resetting ...
U-Boot SPL 2013.01.01 (Oct 12 2016 - 10:38:03)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz(...reboots automatically)
after the command, md fails as follows:
command
md.b FF200000 1
log
ff200000:
(freezes)
Thank you!