Multi-Processor Implimentation in Platform Designer

I have two boards I purchased from Terasic, one is the DE1-SoC and the other is the Apollo S10 SOM. The first one has the Dual Core A9 processor, the latter has Quad Core A53.

The reference designs by Terasic includes a GHRD. In each case, when I open up Platform Designer and load in the top design.qsys, I do not see in the component editor that there is more then 1 core available to map out my signals to custom IP I implement in the FPGA.

I wish to have multiple cores in my design, and to implment the code with the Pthread command in Linux.

Do I have to include multiple instances of the HPS Core in Platform Designer? When I add the physical core to Platform Designer, and click on the component, view the block diagram, the rest of the cores are misssing, and there is nothing in the component editor to instantiate multiple cores. The reference design, although functional and works, I plan on using the extra cores to map to more extensive custom IP in the FPGA that I cannot otherwise map out on one core, or that I wish to impliment in parallel.

This brings up a host of questions, if I do instantiate another HPS core in Platform Designer, how will I know which core maps to the Pthread command to control my custom IP (lets say the Apollo S10 which has 4 cores)?

I do not have permission from Terasic to publish there GHRD, but it is included on the CD available on the Terasic website.