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Hi @EBERLAZARE_I_Intel ,
Thank you for the reply.
I have followed the flow and now linux is running on HPS. But the hps2fpga bridges are not enabled. I have check /sys/class/fpga_bridges directory and it is empty.
I think since the .dtb file (from linux source) we have, is a bare minimum device tree file and it explain only the harden device connected to hps, so it doesn't describe the soft IPs connected to hps over hps2fpga bridge or lwhps2fpga bridge. screen shot of soc node defined in dtsi file for arria10 in linux source is attached here. It shows that HPS_FPGA bridges are not defined.
Actually, I am trying to integrated open source NVIDIA's Deep Learning Accelerator (NVDLA) with hps. soft IP of NVDLA is connected to hps in platform designer via lwhps2fpga bridge as show in the screen shot attached here.
After device tree is create for this custom project, I need to build nvdla Kernel Module Driver (KMD) with Linux source code, before compiling linux kernel into compressed image (zImage). This kmd is also using a reseved memory region of 1 GB for running NVDLA jobs.
So in conclusion I have three main issues I need help with.
1. Creating device Device driver for any custom project.
I have tried to follow a tutorial given on rocketboard.org for creating device using sopc2dtc command and board.xml files. I have contacted Terasic for board xml files for HAN Pilot Platform but they told me that they don't have xml files for Han. Still I tried using xml files of arria10 SOCkit but it didn't work.
2. editing final device tree file to add node for reserved memory.
3. How build KMD with linux kernel source code.
I have also uploaded the above screen shots as attachment with this comment for your reference.
Hi,
1. The xml files should be used from your project which is generated by Quartus, it is located in the "hps_isw_handoff" folder.
2. & 3. Since this is a third party IP, we recommend that you seek the provider of the IP for Linux device tree build and configuration.