Forum Discussion

aucamera1's avatar
aucamera1
Icon for New Contributor rankNew Contributor
6 months ago

HPS f2sdram read/write errors

I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through th...
general
aucamera1's avatar
aucamera1
Icon for New Contributor rankNew Contributor
5 months ago
  1. We started with the GSRD, but we've made changes since then.
  2. We're booting all the way into Linux.
  3. The bridge enable command is present in the U-BOOT boot arg configuration. 

 

    We are using HPS-first boot configuration. Is it possible our custom logic is trying to send transactions before the bridge enable has completed its work?

Yoda_Altera's avatar
Yoda_Altera
Icon for New Contributor rankNew Contributor
5 months ago

Ok.  Great.  So, I assume you program the fabric from Linux, right?  If so, then bridge enable will be completed well before the Fabric is programmed (of course).

Now, you have probably already done this, but just to make sure I am clear, please read/write from your custom logic to address: 

0x00_8000_0000 (0GB physical DDR)

0x08_8000_0000 (2GB physical DDR)

0x09_0000_0000 (4GB physical DDR)

0x09_8000_0000 (6GB physical DDR)

 

  • aucamera1's avatar
    aucamera1
    Icon for New Contributor rankNew Contributor
    5 months ago

    Hi Yoda_Altera​ 

    Hi Yoda,

    Attached are the Read signals from a read cycle to the SDAM.  Here I’m showing 00_8000_0000 and 08_8000_0000 address, but the “9” addresses behave the same

    thanks

     

    • Yoda_Altera's avatar
      Yoda_Altera
      Icon for New Contributor rankNew Contributor
      5 months ago

      Hi aucamera1,

      Thanks for those snapshots.  Let me do some investigation here and I will get back to you soon.

      • Yoda_Altera's avatar
        Yoda_Altera
        Icon for New Contributor rankNew Contributor
        5 months ago

        Hi Aucamera1,

        Please try setting the AxUSER to 0xE0 for F2SDRAM transactions:

        0xE0 = SDRAM direct

        0x04 = CCU