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aucamera1's avatar
aucamera1
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6 months ago

HPS f2sdram read/write errors

I'm using the Agilex 5 devlopment board and trying to write to the HPS SDRAM with custom logic. I'm already able to write to the other SDRAM (DDR4) on the board with my custom logic going through th...
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Yoda_Altera's avatar
Yoda_Altera
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5 months ago

Hi aucamera1,

  1. First, lets make sure you are enabling the bridges properly. 
    1. Are you using the Altera GSRD?
    2. If so,
      1. are booting up to U-Boot and then stopping there to do your reads/writes from your custom logic? 
      2. Or are you booting all the way to Linux to then do your reads/writes from your custom logic?

    3. Please see U-boot commands list at:

      1. https://altera-fpga.github.io/rel-25.3.1/embedded-designs/agilex-5/e-series/premium/boot-examples/ug-linux-boot-agx5e-premium/#boot-from-sd-card_1

    4. In the above U-Boot commands list, Here is the boot command that runs bridge enable
      1. CONFIG_BOOTCOMMAND="load mmc 0:1 \${loadaddr} ghrd.core.rbf; fpga load 0 \${loadaddr} \${filesize};bridge enable; mmc rescan; fatload mmc 0:1 82000000 Image;fatload mmc 0:1 86000000 socfpga_agilex5_socdk.dtb;setenv bootargs console=ttyS0,115200 root=\${mmcroot} rw rootwait;booti 0x82000000 - 0x86000000"
    5. Please make sure you run bridge enable command before trying to read/write from your custom logic.

Regards,

Yoda (Jeff)

aucamera1's avatar
aucamera1
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5 months ago
  1. We started with the GSRD, but we've made changes since then.
  2. We're booting all the way into Linux.
  3. The bridge enable command is present in the U-BOOT boot arg configuration. 

 

    We are using HPS-first boot configuration. Is it possible our custom logic is trying to send transactions before the bridge enable has completed its work?

  • Yoda_Altera's avatar
    Yoda_Altera
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    5 months ago

    Ok.  Great.  So, I assume you program the fabric from Linux, right?  If so, then bridge enable will be completed well before the Fabric is programmed (of course).

    Now, you have probably already done this, but just to make sure I am clear, please read/write from your custom logic to address: 

    0x00_8000_0000 (0GB physical DDR)

    0x08_8000_0000 (2GB physical DDR)

    0x09_0000_0000 (4GB physical DDR)

    0x09_8000_0000 (6GB physical DDR)

     

    • aucamera1's avatar
      aucamera1
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      5 months ago

      Hi Yoda_Altera​ 

      Hi Yoda,

      Attached are the Read signals from a read cycle to the SDAM.  Here I’m showing 00_8000_0000 and 08_8000_0000 address, but the “9” addresses behave the same

      thanks

       

      • Yoda_Altera's avatar
        Yoda_Altera
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        5 months ago

        Hi aucamera1,

        Thanks for those snapshots.  Let me do some investigation here and I will get back to you soon.