New ContributorHow to connect2 Avalon MM masters to 1 MM slave
I am going to be using the EMIF IP to connect to a DDR4 memory. I have 2 MM masters trying to access the memory. I am trying to come up with a design in Qsys and cannot understand how to go about this. Essentially i am looking for something like an AXI interconnect in vivado where i could have 2 slave ports in and 1 master port out of the interconnect. But i guess in quartus the interconnect is used by default. How do i connect both my entities to the EMIF IP?
Yes, in Platform Designer (Qsys) you simply connect both masters to the same slave interface of the IP. You can do this in the Connections panel of the System Contents tab (clicking the correct dots) or select the slave interface there and open the Connections tab from the View menu and use the checkboxes there.
