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ppp2's avatar
ppp2
Icon for New Contributor rankNew Contributor
4 months ago

FPGA-HPS DDR contention on Agilex5 SoC while running Linux: efficient data exchange strategies

I’m working on a device based on an Agilex5 SoC with HPS, which is new hardware for me.

The FPGA and HPS will share DDR memory, and Linux will be running on the HPS at the same time. The FPGA will be streaming a high volume of data that needs to be consumed by a userspace program on the CPU.

I’m concerned that if the FPGA saturates the memory interconnect, the kernel might struggle to perform memory allocations or other transactions for other threads.

Has anyone encountered this kind of bus contention on Agilex/SoC platforms? What strategies do you use to prevent FPGA traffic from starving HPS memory accesses while Linux is running? Also, is there any recommendation / strategy for an FPGA and a userspace program on Linux to exchange data efficiently and safely in this kind of setup?

Sw Development

2 Replies

  • JitLoonL_Altera's avatar
    JitLoonL_Altera
    Icon for Occasional Contributor rankOccasional Contributor
    4 months ago

    Hi @ppp2 ,


    Yeah, you’re right to be concerned. On Agilex 5 SoCs, if your FPGA is streaming a lot of data straight into DDR, it can hog the memory interconnect and slow down Linux or even cause memory allocations to stall. I’ve run into similar issues before.

    A few things that usually help:

    • Throttle the FPGA traffic via HPS-FPGA bridges: Use the bridges’ QoS settings or limit burst sizes on the FPGA side so the HPS always gets guaranteed memory bandwidth. This prevents the FPGA from starving the CPU.

    • DMA + double buffers: Don’t let userspace hit the memory directly. Stream data via FPGA-to-HPS DMA using ping-pong or circular buffers. Userspace programs can then safely read from these buffers.

    • Kernel mediation: A small kernel driver exposing these buffers via mmap or a character device keeps everything safe and avoids contention on DDR.

    • Sync with userspace: Use interrupts, eventfd, or similar signaling mechanisms to notify userspace when new data is ready, rather than busy-waiting, which can also hammer the memory bus.

    The key idea is to control FPGA memory access through the bridges and have a structured path for Linux/userspace to consume the data efficiently without blocking the HPS.

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 months ago

    Hi


    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Regards

    JIngyang, Teh