sgr
New Contributor
3 years agoFPGA DDR interface (EMIF IP)
Hi all,
We have 8GB of FPGA DDR memory space, and i want to access full 8 GB of DDR memory space.
I have tried with one EMIF IP and i was able to access the DDR memory space up to 4GB
Question 1
Since we have 8 GB of DDR memory space can we use 2 EMIF IP to access the whole 8 GB, is there any limitation for that ?
Question 2
If we use 2 EMIF IP each of 2 GB, we are able to access only 2GB, entire 4GB is not accessible. Is there any inputs from your side to use 2 EMIF IP ?
Please provide some inputs from your side.
Thankyou all