FPGA DDR interface (EMIF IP)

Hello!

I need some other information for checking your DDR interface.

Please provide the information of the following:

1. Which Quartus version and OS environment that you used?
2. Which device OPN that you used in the your design?
3. What is the memory spec that you have?
4. Can you share the memory device datasheet here?
5. Can you take some snapshots of the EMIF IP setting GUI?

Question 1

Since we have 8 GB of DDR memory space can we use 2 EMIF IP to access the whole 8 GB, is there any limitation for that ?

• 2 EMIF IP to access 1 memory device may not be possible unless the memory and device are support it. You can provide the information that I've requested as above for checking the features available.

Question 2

If we use 2 EMIF IP each of 2 GB, we are able to access only 2GB, entire 4GB is not accessible. Is there any inputs from your side to use 2 EMIF IP ?

• I will come back to this question after getting the information of the memory and device.

Thanks!

Regards,

Adzim