delay problem
Hi there!
I will be very grateful if someone solve my problem. It's seem to be a basic problem, however I cound't fine a proper way to explane it. I am very wondering why.
Program:
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module Tfine(clk_50M,clk,clkPLL,SampleClk,trig,stop,push,t,s);
input clk_50M,push;
output clk,clkPLL,SampleClk;
output reg trig,stop = 1'b0;
wire HIGH = 1'b1;
wire LOW = 1'b0;
output wire t,s;
PLL p1(.refclk(clk_50M),.rst(LOW),.outclk_0(SampleClk),.outclk_1(clk),.outclk_2(clkPLL));
assign t = (~push)&clkPLL;
assign s = t&clk;
always@(posedge t)begin
if(push == 1'b0) trig = 1'b1;
else trig = 1'b0;
end
always@(posedge s)begin
if(push == 1'b0) stop = 1'b1;
else stop = 1'b0;
end
endmodule
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Waveform on signal tap:
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My problem is I don't know why there is a delay between posedge clk and signal s. I use a similar way to descript s and t. When clkPLL rise, t will rise immediately. However, I cound't got a same result on t.
Does your design meet timing?
If you simulate your design, do you see the same behavior?
Regards,
Richard Tan