delay problem

Hello,

I presume, the design won't meet timing. The effect seen in the SignalTap recording is however of different kind. The obeserved "delay" is caused by the simple fact, that all signals are sampled by 100 MHz SampleClk. SignalTap wave form has only 10 ns time resolution.

It's just not clear at first sight, why t edge is seen immediately and s edge one sample later. We don't know the exact PLL parameters, particularly phase relation of SampleClk, clk and clkPLL, the behaviour may be expectable by design or caused by arbitrary delay skew.

Obviously simulation will show a quite different picture, displaying signals with simulation time step.

Best regards
Frank