DDR3 Board parameters

Question

Hi Everyone,Im working on a cyclone V device with DDR3 MICRON vendor.we are now trying to fill up the board parameters in the setup and hold derating section.we have some board simulation data from the board designer layout but we don't sure what value to take. The tis,tih,tds,tdh in the simulation output are margin from the minimum setup and hold.Do we need to add this margin value to ddr spec tis and tih ?tis,tih: tds,tdh:thanks for your answer in advance,BR,Ram.

zhenruan · Answer

Hi Ram,Please refer to the link below for the settings:https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/slew-rate-setup-hold-and-derating-c.htmlRegards,Aaron

ramsoffer_123 · Answer

hi,it helps.still working on it.thanks,BR,Ram.

wz2 · Answer

Hi there,I wanted to check if you have any further questions or concerns. If not, I will go ahead and mark this issue as resolved.Additionally, we would greatly appreciate it if you could take a moment to fill out our survey. Your feedback is valuable to us and helps us improve our support quality.Thank you for your time and cooperation.Best regards,WZ

Forum Discussion

DDR3 Board parameters

3 Replies

Recent Discussions

Unique ID registers in Cyclone V

Audio interface with Agilex 5 A5ED065BB32AI4S

Operating system kernel-level FPGA bridge communication

Routing PL DDR to PS

Validating ECC Functionality on Custom Agilex 5 SOM in Linux Kernel