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BrianSune_Froum
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5 months ago

Cyclone V HPS bus - FPGA-to-SDRAM

Dear Intel, and all, Brian here and there is a very puzzling documenting on: https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/fpga-to-hps-sdram-access.html Based on the 256 bi...
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BrianSune_Froum
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5 months ago

@ShoH_Altera

No you still misunderstand what i am trying to point out.

I do clearly known the HPS can only create "1" 256 bit AXI3 R/W interface based on the fixed HPS interface.

Either from the HPS Qsys or the link I enclosed from first place.

However, based on the link, the table mentioned "possible port utilization".

Why the AXI3 64bit only support 1 set?

With the above statement AXI3 allow what configurations?

What I am trying to pointed out is this information is labeled wrongly and very puzzling from first place.