Cyclone V HPS bus - FPGA-to-SDRAM

Hi @BrianSune_Froum ,

Thanks for you posting.

First, Let me confirm how FPGA-to-SDRAM bridge can be configured.

"There is a maximum of six command ports, four 64-bit read data port and four 64-bit

write data port."

These three types of ports can be combined to form multiple Avalon-MM/AXI interfaces.

The table 5 to which you refer shows which ports and how many are required for each interface.

For example : You can configure

1x 64bit AXI (2:CommandPorts, 1:ReadPort, 1:WritePort)

1x 128bit Avalon-MM Write Only (1:CommandPort, 0:ReadPort, 2:WritePorts)

1x 128bit Avalon-MM Read Only (1:CommandPort, 2:ReadPorts, 0:WritePort)

1x 64bit Avalon-MM Bidirectional (1xCommandPort, 1xReadPort, 1xWritePort)

The above configuration utilizes 4:CommandPorts, 4:ReadPorts, 4:WritePorts. (2:CommandPorts are un-used.)

Is there something strange or wrongly labeled?

Regards,