Forum Discussion
ContributorCustom board on Cyclone V HPS SDRAM preloader test
The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
UBOOT memory normal test also passed w/o any errors.
So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.
No matter it is /w or /wo the board settings no drop no crash no stuck.
So the case ends here.
ContributorI think you had misread my descriptions on previous post.
What I am pointing out it that the official development board from altera itself already violated the design rules.
If leveling is not supported then as you mentioned clearly it is not allow to use fly-by from first place.
But according to the allegro design file from the board design.
With this image of the official altera design layout. it already violated the Balance-T design.
There is a ECC at one end but not middle and it does not follow a T branch design but a fly-by hybird layout.
So please explain why this is the case.
