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BrianSune_Froum's avatar
BrianSune_Froum
Icon for Contributor rankContributor
1 year ago
Solved

Custom board on Cyclone V HPS SDRAM preloader test

Dear Intel and all, Apart from the DDR3 topology. The first stage testing shows a very puzzling behavior. BOARD : Altera SOCFPGA Cyclone V Board CLOCK: EOSC1 clock 50000 KHz CLOCK: EOSC2 clock...
Board Debug
  • BrianSune_Froum's avatar
    BrianSune_Froum
    1 year ago

    The final result is that even with a fly-by routed topology there are no issue on both 1.5V and 1.35V DDR3 DDR3L.
    The MT41K128M16 /w 1k page size shows no sanity issue on memtest stresapptest on distro.
    UBOOT memory normal test also passed w/o any errors.

    So after short testing we can only assume there are inherent bug on Quartus 18.1? or HPS IP.

    No matter it is /w or /wo the board settings no drop no crash no stuck.

    So the case ends here.

KianHinT_altera's avatar
KianHinT_altera
Icon for Frequent Contributor rankFrequent Contributor
1 year ago

Hi Brian,

May I know what are the device tree settings for U-boot? Could you provide us the devicetree file that you're using?

Thanks

Regards

Kian

  • BrianSune_Froum's avatar
    BrianSune_Froum
    Icon for Contributor rankContributor
    1 year ago

    @khtan

    I think you are referring to the kernel dts?

    For U-Boot I never touch it because I am using Quartus 18.1

    For that flow bsp-editor will create the MakeFile.

    Once it runs make -all and make uboot

    It will unzip the uboot zip from local install folder rather like newest FPGA device form GIT.

    For kernel dts

    ```

    // SPDX-License-Identifier: GPL-2.0
    /*
    * Copyright Altera Corporation (C) 2015. All rights reserved.
    */
    #include "socfpga_cyclone5_b.dtsi"
    //#include <dt-bindings/gpio/gpio.h>
    / {
    model = "Custom Board Cyclone V Soc";
    compatible = "altr,socfpga-cyclone5", "altr,socfpga";
    aliases {
    ethernet0 = &gmac1;
    };
    chosen {
    bootargs = "earlyprintk";
    stdout-path = "serial0:115200n8";
    };
    memory@0 {
    name = "memory";
    device_type = "memory";
    reg = <0x0 0x20000000>; /* 512MB */
    };

    ```